The present invention generally relates to adaptive timing recovery, and more specifically, to a method and system for providing improved adaptive timing recovery for low power applications.
Adaptive timing recovery has been in use for years in electronic equipment. In a conventional piece of electronic equipment that utilizes adaptive timing recovery, adaptive timing recovery is typically accomplished using a full rate timing error generation function and a loop filter.
Conventional adaptive timing recovery suffers from a number of problems. For example, conventional implementation of adaptive timing recovery generally requires significant power consumption. The myriad types of problems associated with high level of power consumption in electronic devices are well known. In addition, conventional circuitry used to implement adaptive timing recovery does not scale well when multiple timing recovery loops are used on one chip for multiple channels. Furthermore, such circuitry is unable to adapt the update rate based on timing loop lock status.
Hence, it would be desirable to have a method and system that is capable of providing adaptive timing recovery at a reduced the level of power consumption.